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Document revision history
27 Document revision history
The following table provides a revision history for this document.
Table 68. Document revision history
Rev.
No.
3
2
Date
04/2014
09/2012
Substantive Change(s)
? Re-introduced Section 8.3.3, “IEEE 1588 DC Specifications and Section 8.3.4, “IEEE 1588 AC
Specifications
? In Table 55 , swapped CLK13 and CLK14.
? In Table 55 , removed the following test signals, as there are no corresponding use cases:
– ECID_TMODE_IN
– BOOT_ROM_ADDR[2] to BOOT_ROM_ADDR[12]
– BOOT_ROM_RDATA[0] to BOOT_ROM_RDATA[31]
– BOOT_ROM_MOD_EN, BOOT_ROM_RWB, BOOT_ROM_XFR_WAIT, BOOT_ROM_XFR_ERR
– UC1_RM, UC2_RM, UC3_RM, UC5_RM, UC7_RM, AND URM_TRIG
– TPR_SYS_AAD[0] to TPR_SYS_AAD[15]
– TPR_SYS_SYNC, TPR_SYS_DACK
– QE_TRB_0, QE_TRB_1
– PLLCZ_CORE_CLKIN
– JTAG_BISE, JTAG_PRPGPS, JTAG_BISR_TDO_EN
– CLOCK_XLB_CLOCK_OUT
– PD_XLB2MG_DDR_CLOCK
? In Table 55 , changed the following signal names as only QE-Based Fast Ethernet Controller is present
in this device:
– TSEC_TMR_TRIG1 to FEC_TMR_TRIG1
– TSEC_TMR_TRIG2 to FEC_TMR_TRIG2
– TSEC_TMR_CLK to FEC_TMR_CLK
– TSEC_TMR_GCLK to FEC_TMR_GCLK
– TSEC_TMR_PP1 to FEC_TMR_PP1
– TSEC_TMR_PP2 to FEC_TMR_PP2
– TSEC_TMR_PP3 to FEC_TMR_PP3
– TSEC_TMR_ALARM1 to FEC_TMR_ALARM1
– TSEC_TMR_ALARM2 to FEC_TMR_ALARM2
– FEC3_TMR_TX_ESFD to FEC2_TMR_TX_ESFD
– FEC3_TMR_RX_ESFD to FEC2_TMR_RX_ESFD.
? In Table 18 , added parameteres t LALEHOV ,, t LALETOT , and t LBOTOT and made the corresponding updates
in Figure 8
? In Figure 3 , replaced "32 X tSYS_CLK_IN" with "32 X tSYS_CLK_IN/PCI_SYNC_IN.
1
08/2011
?
?
?
?
?
Updated QUICC Engine frequency in Table 5 .
Updated QUICC Engine frequency from 200 MHz to 233 MHz in Table 63 .
Updated CEPMF and CEDF as per new QE frequency in Table 63 .
Updated QUICC Engine frequency to 233 MHz in Table 66 .
Corrected LCCR to LCRR for all instances.
0
03/2011
Initial Release.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
80
Freescale Semiconductor
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